SPEECH RECOGNITION SYSTEM BASED POWERED DEVICES CONTROL SYSTEM
CIRCUIT
DIAGRAM DESCRIPTION
The above circuit the diagram shows various connections used in this project, now let us see the
working principle of this circuit,
The microcontroller used here is 8 bit RISC architecture PIC16F877A which has a
inbuilt 10 bit ADC, the controller receives the analog signals from the
amplifier with the help of ADC converts to digital and process it.
Three
toggle keys are interfaced to PORTC of the microcontroller; the keys are used
for increasing and decreasing the speed level of the motor.
The speed of the controller is 16MHz generated by a Crystal
In the speech recognition kit, the voice messages are recorded predefined
by using keypads. This kit is interfaced with the microcontroller. When the
message is retrieved the microcontroller detects if it is correct means the
microcontroller will turn ON / OFF the relays. In the relay, we can connect
any external devices.
The relay is an electromechanical
device.It operated on +12V DC supply When a current flows through the coil,
the resulting magnetic field attracts an armature that is mechanically linked
to a moving contact. When the current to the coil is switched off, the armature
is returned by a force approximately half as strong as the magnetic force to
its relaxed position. This condition performed by normal BC 547 transistors.
When the transistor is ON the relay will be ON otherwise it will be always OFF
MICROCONTROLLER PIC16F877A
Introduction:
High-Performance RISC CPU:
v Only
35 single-word instructions to learn
v All
single-cycle instructions except for program branches, which are two-cycle
v Operating
speed: DC – 20 MHz clock input
DC – 200 ns instruction cycle
v Up
to 8K x 14 words of Flash Program Memory,
v Up
to 368 x 8 bytes of Data Memory (RAM),
v Up
to 256 x 8 bytes of EEPROM Data Memory
v Pinout
compatible to other 28-pin or 40/44-pin
v PIC16CXXX
and PIC16FXXX microcontrollers
Peripheral Features:
v Timer0:
8-bit timer/counter with 8-bit Prescaler
v Timer1:
16-bit timer/counter with Prescaler can be incremented during Sleep via
external crystal/clock
v Timer2:
8-bit timer/counter with 8-bit period register, Prescaler and postscaler
v Two
Capture, Compare, PWM modules
v Capture
is 16-bit, max. resolution is 12.5 ns
v Compare
is 16-bit, max. resolution is 200 ns
v PWM
max. resolution is 10-bit Synchronous Serial Port (SSP) with SPI™
v (Master
mode) and I2C™ (Master/Slave) Universal Synchronous Asynchronous Receiver
v Transmitter
(USART/SCI) with 9-bit address detectionParallel Slave Port (PSP) – 8 bits wide
with external RD, WR and CS controls (40/44-pin only)
v Brown-out
detection circuitry for Brown-out Reset (BOR)
Analog Features:
v 10-bit,
up to 8-channel Analog-to-digital converter (A/D)
v Brown-out
Reset (BOR)
Analog Comparator module with:
v Two
analog comparators Programmable on-chip voltage reference (VREF) module Programmable
input multiplexing from device inputs and internal voltage reference Comparator
outputs are externally accessible
Special Microcontroller Features:
v 100,000
erase/write cycle Enhanced Flash program memory typical
v 1,000,000
erase/write cycle Data EEPROM memory typical
v Data
EEPROM Retention > 40 years
v Self-reprogrammable
under software control
v In-Circuit
Serial Programming™ (ICSP™) via two pins
v Single-supply
5V In-Circuit Serial Programming
v Watchdog
Timer (WDT) with its own on-chip RC oscillator for reliable operation
v Programmable
code protection
v Power
saving Sleep mode
v Selectable
oscillator options
v In-Circuit
Debug (ICD) via two pins
CMOS Technology:
v Low-power,
high-speed Flash/EEPROM technology
v Fully
static design
v Wide
operating voltage range (2.0V to 5.5V)
v Commercial
and Industrial temperature ranges
v Low-power
consumption
The high performance of the PICmicro
devices can be attributed to a number of architectural features commonly found
in RISC microprocessors. These include:
• Harvard architecture
• Long Word Instructions
• Single Word Instructions
• Single Cycle Instructions
• Instruction Pipelining
• Reduced Instruction Set
• Register File Architecture
• Orthogonal (Symmetric) Instructions
Figure shows a simple core
memory bus arrangement for Mid-Range MCU devices.
Harvard Architecture
Harvard architecture has
the program memory and data memory as separate memories and is accessed from
separate buses. This improves bandwidth over traditional von Neumann
architecture in which program and data are fetched from the same memory using
the same bus. To execute an instruction, a von Neumann machine must make one or
more (generally more) accesses across the 8-bit bus to fetch the instruction.
Then data may need to be fetched, operated on, and possibly written. As can be
seen from this description, that bus can be extremely congested. While with
Harvard architecture, the instruction is fetched in a single instruction cycle
(all 14-bits). While the program memory is being accessed, the data memory is on
an independent bus and can be read and written. These separated buses allow one
instruction to execute while the next instruction is fetched. A comparison of
Harvard vs. von-Neumann architectures is shown in Figure.
SPEECH RECOGNITION IC
The speech recognition system
is a completely assembled and easy to use programmable speech recognition
circuit. Programmable, in the sense that you train the words (or vocal
utterances) you want the circuit to recognize. This board allows you to
experiment with many facets of speech recognition technology. It has 8-bit data
out which can be interfaced with any microcontroller for further development.
Some of the interfacing applications which can be made are controlling home appliances,
robotics movements, Speech Assisted technologies, Speech to text translation,
and many more.
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